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1 april 22, 2002 u634h256xsa automotive powerstore 32k x 8 nvsram pin configuration pin description top view 1 vcap vccx 32 2 a14 hsb 31 4 a7 a13 29 5 a6 a8 28 3 a12 w 30 6 a5 a9 27 7 a4 a11 26 8 a3 g 25 12 a0 dq7 21 9 n.c. n.c. 24 10 a2 a10 23 11 a1 e 22 13 dq0 dq6 20 14 dq1 dq5 19 sop signal name signal description a0 - a14 address inputs dq0 - dq7 data in/out e chip enable g output enable w write enable vccx power supply voltage vss ground vcap capacitor hsb hardware controlled store/busy high-performance cmos non- volatile static ram 32768 x 8 bits 35 ns access time 15 ns output enable access time i cc = 15 ma at 200 ns cycle time automatic store to eeprom on power down using external capacitor hardware or software initiated store (store cycle time < 10 ms) automatic store timing 10 5 store cycles to eeprom 10 years data retention in eeprom automatic recall on power up software recall initiation (recall cycle time < 20 s) unlimited recall cycles from eeprom single 5 v 10 % operation operating temperature ranges: - --40 to 125 c cecc 90000 quality standard esd characterization according mil std 883c m3015.7-hbm (classification see ic code numbers) package: sop32 (300 mil) the u634h256xsa has two sepa- rate modes of operation: sram mode and nonvolatile mode. in sram mode, the memory operates as an ordinary static ram. in non- volatile operation, data is transfer- red in parallel from sram to eeprom or from eeprom to sram. in this mode sram functions are disabled. the u634h256xsa is a fast static ram (35 ns), with a nonvolatile electrically erasable prom (eeprom) element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resi- des in eeprom. data transfers from the sram to the eeprom (the store operation) take place automatically upon power down using charge stored in an external 100 f capacitor. transfers from the eeprom to the sram (the recall operation) take place automatically on power up. the u634h256xsa combines the high performance and ease of use of a fast sram with nonvolatile data integrity. store cycles also may be initia- ted under user control via a soft- ware sequence or via a single pin (hsb ). once a store cycle is initiated, further input or output are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. recall cycles may also be initia- ted by a software sequence. internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvola- tile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. 15 dq2 dq4 18 16 vss dq3 17 features description
2 april 22, 2002 u634h256xsa block diagram operating mode e hsb w g dq0 - dq7 standby/not selected h h ** high-z internal read l h h h high-z read l h h l data outputs low-z write l h l * data inputs high-z truth table for sram operations a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stre ss rating only, and functional operation of the device at condition above those indicated in the operational sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings a symbol min. max. unit power supply voltage v cc -0.5 7 v input voltage v i -0.3 v cc +0.5 v output voltage v o -0.3 v cc +0.5 v power dissipation p d 1w operating temperature t a -40 125 c storage temperature t stg -65 150 c characteristics all voltages are referenced to v ss = 0 v (ground). all characteristics are valid in the power supply voltage range and in the operating temperature range specified. dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of v i ,as well as input levels of v il = 0 v and v ih = 3 v. the timing reference level of all input and output signals is 1.5 v, with the exception of the t dis -times and t en -times, in which cases transition is measured 200 mv from steady-state voltage. * h or l eeprom array 512 x (64 x 8) store recall sram array 512 rows x 64 x 8 columns a0 - a13 store/ recall control hsb row decoder v ccx v ss v cap g e w software detect power control v ccx v cap a5 a6 a7 a8 a9 a11 a12 a13 a14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 column i/o column decoder a0 a1 a2 a3 a4 a10 input buffers
3 april 22, 2002 u634h256xsa b: v cc reference levels throughout this datasheet refer to v ccx if that is where the power supply connection is made, or v cap if v ccx is con- nected to ground. c: i cc1 and i cc3 are depedent on output loading and cycle rate. the specified values are obtained with outputs unloaded. the current i cc1 is measured for write/read - ratio of 1/2. i cc2 is the average current required for the duration of the store cycle (store cycle time). d: bringing e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. see mode selection able. the current i cc(sb)1 is measured for write/read - ratio of 1/2. dc characteristics symbol conditions min. max. unit operating supply current c i cc1 v cc v il v ih t c = 5.5 v = 0.8 v = 2.2 v = 35 ns 80 ma average supply current during store c i cc2 v cc e w v il v ih = 5.5 v 0.2 v v cc -0.2 v 0.2 v v cc -0.2 v 7ma average supply current during powerstore cycle i cc4 v cc v il v ih = 4.5 v = 0.2 v v cc -0.2 v 4ma standby supply current d (cycling ttl input levels) i cc(sb)1 v cc e t c = 5.5 v = v ih = 35 ns 38 ma operating supply current at t cr = 200 ns c (cycling cmos input levels) i cc3 v cc w v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 15 ma standby supply current d (stable cmos input levels) i cc(sb) v cc e v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 4ma recommended operating conditions symbol conditions min. max. unit power supply voltage b v cc 4.5 5.5 v input low voltage v il -2 v at pulse width 10 ns permitted -0.3 0.8 v input high voltage v ih 2.2 v cc +0.3 v
4 april 22, 2002 u634h256xsa dc characteristics symbol conditions min. max. unit output high voltage output low voltage v oh v ol v cc i oh i ol = 4.5 v =-4 ma = 8 ma 2.4 0.4 v v output high current output low current i oh i ol v cc v oh v ol = 4.5 v = 2.4 v = 0.4 v 8 -4 ma ma input leakage current high low i ih i il v cc v ih v il = 5.5 v = 5.5 v = 0 v -1 1 a a output leakage current high at three-state- output low at three-state- output i ohz i olz v cc v oh v ol = 5.5 v = 5.5 v = 0 v -1 1 a a sram memory operations e: parameter guaranteed but not tested. f: device is continuously selected with e and g both low. g: address valid prior to or coincident with e transition low. h: measured 200 mv from steady state output voltage. no. switching characteristics read cycle symbol min. max. unit alt. iec 1 read cycle time f t avav t cr 35 ns 2 address access time to data valid g t av q v t a(a) 35 ns 3 chip enable access time to data valid t elqv t a(e) 35 ns 4 output enable access time to data valid t glqv t a(g) 15 ns 5e high to output in high-z h t ehqz t dis(e) 13 ns 6g high to output in high-z h t ghqz t dis(g) 13 ns 7e low to output in low-z t elqx t en(e) 5ns 8g low to output in low-z t glqx t en(g) 0ns 9 output hold time after address change t axqx t v(a) 3ns 10 chip enable to power active e t elicch t pu 0ns 11 chip disable to power standby d, e t ehiccl t pd 35 ns
5 april 22, 2002 u634h256xsa read cycle 1: ai-controlled (during read cycle: e = g = v il , w = v ih ) f read cycle 2: g -, e -controlled (during read cycle: w = v ih ) g no. switching characteristics write cycle symbol min. max. unit alt. #1 alt. #2 iec 12 write cycle time t avav t avav t cw 35 ns 13 write pulse width t wlwh t w(w) 25 ns 14 write pulse width setup time t wleh t su(w) 25 ns 15 address setup time t avwl t avel t su(a) 0ns 16 address valid to end of write t avwh t aveh t su(a-wh) 25 ns 17 chip enable setup time t elwh t su(e) 25 ns 18 chip enable to end of write t eleh t w(e) 25 ns 19 data setup time to end of write t dvwh t dveh t su(d) 12 ns 20 data hold time after end of write t whdx t ehdx t h(d) 0ns 21 address hold after end of write t whax t ehax t h(a) 0ns 22 w low to output in high-z h, i t wlqz t dis(w) 13 ns 23 w high to output in low-z t whqx t en(w) 5ns t a(a) previous data valid output data valid t cr address valid t v(a) ai (1) (2) (9) ai e g t dis(e) t cr t a(e) t en(e) t en(g) t a(g) t dis(g) output data valid high impedance i cc active standby t pd t pu (1) (3) (4) (5) (7) (6) (8) (10) (11) t a(a) (2) address valid dqi output dqi output
6 april 22, 2002 u634h256xsa l- to h-level undefined h- to l-level i: if w is low and when e goes low, the outputs remain in the high impedance state. j: e or w must be v ih during address transition. write cycle #1: w -controlled j write cycle #2: e -controlled j t h(d) ai e w dqi input dqi output t cw t su(e) t h(a) t w(w) t su(d) t dis(w) t en(w) address valid input data valid high impedance t su(a-wh) (12) (16) (13) (19) (20) (23) (21) t su(a) t h(d) ai e w dqi input dqi output t cw t w(e) t h(a) t su(d) input data valid t su(w) (12) (18) (21) (20) (19) previous data high impedance t su(a) address valid (17) (15) (22) (15) (14)
7 april 22, 2002 u634h256xsa nonvolatile memory operations mode selection k: the six consecutive addresses must be in order listed (0e38, 31c7, 03e0, 3c1f, 303f, 0fc0) for a store cycle or (0e38, 31c7, 03e0, 3c1f, 303f, 0c63) for a recall cycle. w must be high during all six consecutive cycles. see store cycle and recall cycle tables and diagrams for further details. the following six-address sequence is used for testing purposes and should not be used: 0e38, 31c7, 03e0, 3c1f, 303f, 339c. l: i/o state assumes that g v il . activation of nonvolatile cycles does not depend on the state of g . m: hsb initiated store operation actually occurs only if a write has been done since last store operation. after the store (if any) completes, the part will go into standby mode inhibiting all operation until hsb rises. e w hsb a13 - a0 (hex) mode i/o power notes h x h x not selected output high z standby l h h x read sram output data active l l l h x write sram input data active lhh 0e38 31c7 03e0 3c1f 303f 0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active k, l k, l k, l k, l k, l k lhh 0e38 31c7 03e0 3c1f 303f 0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active k, l k, l k, l k, l k, l k x x l x store/inhibit output high z i cc2 /standby m n: t restore starts from the time v cc rises above v switch . o: hsb is an i/o that has a week internal pullup; it is basically an open drain output. it is meant to allow up to 32 u634h256xsa to be ganged together for simultaneous storing. do not use hsb to pullup any external circuitry other than other u634h256xsa hsb pins. no. powerstore power up recall/ hardware controlled store symbol conditions min. max. unit alt. iec 24 power up recall duration n, e t restore 650 s 25 store cycle duration t hlqx t d(h)s v cc > 4.5 v 10 ms 26 hsb low to inhibit on e t hlqz t dis(h)s 1 s 27 hsb high to inhibit off e t hhqx t en(h)s 700 ns 28 external store pulse width e t hlhx t w(h)s 20 ns hsb output low current e,o i hsb ol hsb = v ol 3ma hsb output high current e, o i hsb oh hsb = v il 560 a low voltage trigger level v switch 4.0 4.5 v
8 april 22, 2002 u634h256xsa powerstore and automatic power up recall hardware controlled store dqi output previous data valid hsb t en(h)s t d(h)s data valid t dis(h)s p: t pdstore approximate t d(e)s or t d(h)s ; t delay approximate t dis(h)s . q: after t w(h)s hsb is hold down internal by store operation. r: an automatic recall also takes place at power up, starting when v cc exceeds v switch and takes t restore . v cc must not drop below v switch once it has been exceeded for the recall to function properly. s: once the software controlled store or recall cycle is initiated, it completes automatically, ignoring all inputs. t: noise on the e pin may trigger multiple read cycles from the same address and abort the address sequence. no. software controlled store/ recall cycle symbol min. max. unit alt. iec 29 store/recall initiation time t avav t cr 35 ns 30 chip enable to output inactive s t elqz t dis(e)sr 600 ns 31 store cycle time t elqxs t d(e)s 10 ms 32 recall cycle time r t elqxr t d(e)r 20 s 33 address setup to chip enable t t aveln t su(a)sr 0ns 34 chip enable pulse width s, t t elehn t w(e)sr 25 ns 35 chip disable to address change t t ehaxn t h(a)sr 0ns t w(h)s q (28) (26) (27) (25) high impedance v cap 5.0 v t powerstore power up v switch w dqi power up recall brown out t restor e t restore brown out powerstore (no sram writes) recall (24) (24) no store t pdstore p t delay p
9 april 22, 2002 u634h256xsa u: if the chip enable pulse width is less then t a(e) (see read cycle) but greater than or equal to t w(e)sr , then the data may not be valid at the end of the low pulse, however the store or recall will still be initiated. v: w must be high when e is low during the address sequence in order to initiate a nonvolatile cycle. g may be either high or low throughout. addresses 1 through 6 are found in the mode selection table. address 6 determines whether the u634h256xsa performs a store or recall. w: e must be used to clock in the address sequence for the software controlled store and recall cycles. ai e dqi output t cr t w(e)sr address 1 valid software controlled store/recall cycle t, u, v, w (e = high after store initiation) address 6 (29) (29) t h(a)sr (35) (34) t su(a)sr (33) ai e dqi output t cr t w(e)sr address 1 valid valid address 6 t d(e)s (31) (32) (29) t h(a)sr (35) (34) t su(a)sr (33) t dis(e)sr (30) t h(a)sr (35) t su(a)sr (33) t w(e)sr t h(a)sr (35) (34) t su(a)sr (33) (5) t dis(e) software controlled store/recall cycle t, u, v, w (e = low after store initiation) t dis(e)sr (30) valid high impedance high impedance t d(e)s (31) (32) t d(e)r t d(e)r t cr
10 april 22, 2002 u634h256xsa test configuration for functional check v ccx y v cap v ih v il v ss 480 255 30 pf x v o simultaneous measure- ment of all 8 output pins input level according to the relevant test measurement dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 hsb a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 hsb e w g 5 v a13 a14 x: in measurement of t dis -times and t en -times the capacitance is 5 pf. y: between v cc and v ss must be connected a high frequency bypass capacitor 0.1 f to avoid disturbances. all pins not under test must be connected with ground by capacitors. capacitance e conditions symbol min. max. unit input capacitance v cc v i f t a = 5.0 v = v ss = 1 mhz = 25 c c i 8pf output capacitance c o 7pf example ic code numbers c esd class blank > 2000 v z b > 1000 v z s u634h256 35 a type package operating temperature range a= -40 to 125c access time 35 = 35 ns s = sop (300 mil) c > 500 v the date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. z: esd protection > 1000 and 2000 v under development
11 april 22, 2002 u634h256xsa device operation the u634h256xsa has two separate modes of opera- tion: sram mode and nonvolatile mode. the memory ope- rates in sram mode as a standard fast static ram. data is transferred in nonvolatile mode from sram to eeprom (the store operation) or from eeprom to sram (the recall operation). in this mode sram functions are disabled. store cycles may be initiated under user control via a software sequence or hsb assertion and are also auto- matically initiated when the power supply voltage level of the chip falls below v switch . recall operations are automatically initiated upon power up and may also occur when the v ccx rises above v switch , after a low power condition. recall cycles may also be initiated by a software sequence. sram read the u634h256xsa performs a read cycle whenever e and g are low and hsb and w are high. the address specified on pins a0 - a14 determines which of the 32768 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t cr . if the read is initiated by e or g , the outputs will be valid at t a(e) or at t a(g) , whichever is later. the data outputs will repeatedly respond to address changes within the t cr access time without the need for transition on any control input pins, and will remain valid until another address change or until e or g is brought high or w or hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq0 - 7 will be written into the memory if it is valid t su(d) before the end of a w controlled write or t su(d) before the end of an e con- trolled write. it is recommended that g is kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t dis(w) after w goes low. automatic store during normal operation, the u634h256xsa will draw current from v ccx to charge up a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v ccx pin drops below v switch , the part will automatically disconnect the v cap pin from v ccx and initiate a store operation. figure 1 shows the proper connection of capacitors for automatic store operation. the charge storage capa- citor should have a capacity of 100 f ( 20 %) at 6 v. each u634h256xsa must have its own 100 f capaci- tor. each u634h256xsa must have a high quality, high frequency bypass capacitor of 0.1 f connected bet- ween v cap and v ss , using leads and traces that are short as possible. this capacitor do not replace the nor- mal expected high frequency bypass capacitor bet- ween the power supply voltage and v ss . in order to prevent unneeded store operations, auto- matic stores as well as those initiated by externally driving hsb low will be ignored unless at least one write operation has taken place since the most recent store cycle. note that if hsb is driven low via external circuitry and no writes have taken place, the part will still be disabled until hsb is allowed to return high. software initiated store cycles are per- formed regardless of whether or not a write opera- tion has taken place. automatic recall during power up, an automatic recall takes place. at a low power condition (power supply voltage < v switch ) an internal recall request may be latched. as soon as power supply voltage exceeds the sense voltage of v switch , a requested recall cycle will automatically be initiated and will take t restore to complete. if the u634h256xsa is in a write state at the end of power up recall, the sram data will be corrupted. to help avoid this situation, a 10 k ? resistor should be connected between w and power supply voltage. software nonvolatile store the u634h256xsa software controlled store cycle is initiated by executing sequential read cycles from six specific address locations. by relying on read cycles only, the u634h256xsa implements nonvolatile opera- tion while remaining compatible with standard 32k x 8 srams. during the store cycle, an erase of the pre- vious nonvolatile data is performed first, followed by a parallel programming of all nonvolatile elements. once a store cycle is initiated, further inputs and outputs are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. to initiate the store cycle the following read sequence must be performed:
12 april 22, 2002 u634h256xsa 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0fc0 (hex) initiate store once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles are used in the sequence, although it is not necessary that g is low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software nonvolatile recall a recall cycle of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to the store initiation. to initiate the recall cycle the following sequence of read opera- tions must be performed: 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0c63 (hex) initiate recall internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. hsb nonvolatile store the hardware controlled store busy pin (hsb ) is connected to an open drain circuit acting as both input and output to perform two different functions. when driven low by the internal chip circuitry it indicates that a store operation (initiated via any means) is in pro- gress within the chip. when driven low by external cir- cuitry for longer than t w(h)s , the chip will conditionally initiate a store operation after t dis(h)s . read and write operations that are in progress when hsb is driven low (either by internal or external circuitry) will be allowed to complete before the store operation is performed, in the following manner. after hsb goes low, the part will continue normal sram operation for t dis(h)s . during t dis(h)s , a transition on any address or control signal will terminate sram operation and cause the store to commence. note that if an sram write is attempted after hsb has been forced low, the write will not occur and the store operation will begin immediately. hardware-store-busy (hsb ) is a high speed, low drive capability bidirectional control line. in order to allow a bank of u634h256xsas to perform synchronized store functions, the hsb pin from a number of chips may be connected together. each chip contains a small internal current source to pull hsb high when it is not being driven low. to decrease the sensitivity of this signal to noise generated on the pc board, it may optionally be pulled to power supply via an external resistor with a value such that the combi- ned load of the resistor and all parallel chip connections does not exceed i hsb ol at v ol (see figure 1 and 2). only if hsb is to be connected to external circuits, an external pull-up resistor should be used. during any store operation, regardless of how it was initiated, the u634h256xsa will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of a store operation, the part will be disabled until hsb actually goes high. hardware protection the u634h256xsa offers hardware protection against inadvertent store operation during low voltage condi- tions. when v cap < v switch , all software or hsb initia- ted store operations will be inhibited. preventing automatic stores the powerstore function can be disabled on the fly by holding hsb high with a driver capable of sourcing 15 ma at v oh of at least 2.2 v as it will have to overpo- wer the internal pull-down device that drives hsb low for 50 ns at the onset of a powerstore . when the u634h256xsa is connected for powerstore operation (see figure 1) and v ccx crosses v switch on the way down, the u634h256xsa will attempt to pull hsb low; if hsb doesn t actually get below v il , the part will stop trying to pull hsb low and abort the powerstore attempt . disabeling automatic stores if the powerstore function is not required, then v cap should be tied directly to the power supply and v ccx should by tied to ground. in this mode, store opera- tion may be triggered through software control or the hsb pin. in either event, v cap (pin 1) must always have a proper bypass capacitor connected to it (figure 2).
13 april 22, 2002 u634h256xsa low average active power the u634h256xsa has been designed to draw signifi- cantly less power when e is low (chip enabled) but the access cycle time is longer than 55 ns. when e is high the chip consumes only standby cur- rent. the overall average current drawn by the part depends on the following items: 1. cmos or ttl input levels 2. the time during which the chip is disabled (e high) 3. the cycle time for accesses (e low) 4. the ratio of reads to writes 5. the operating temperature 6. the power supply voltage level + 0.1 f bypass 100 f 20 % v cap v ss power supply v ccx hsb 10 k ? (optional, figure 1: automatic store operation schematic diagram the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. 32 2 31 4 29 5 28 3 30 6 27 7 26 8 25 12 21 9 24 10 23 11 22 13 20 14 19 15 18 16 17 v cap 5.0 v store inhibit power up v switch t restore recall (24) t disabeling automatic stores: store cycle inhibit and automatic power up recall 1 see description hsb nonvolatile store) 0.1 f bypass v cap v ss power supply v ccx hsb 10 k ? (optional, figure 2: disabeling automatic stores schematic diagram 32 2 31 4 29 5 28 3 30 6 27 7 26 8 25 12 21 9 24 10 23 11 22 13 20 14 19 15 18 16 17 1 see description hsb nonvolatile store)
zentrum mikroelektronik dresden ag grenzstra?e 28 ? d-01109 dresden ? p. o. b. 80 01 34 ? d-01101 dresden ? germany phone: +49 351 8822 306 ? fax: +49 351 8822 337 ? email: sales@zmd.de ? http://www.zmd.de april 22, 2002 u634h256xsa u634h256xsa life support policy zmd products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the zmd product could create a situation where personal injury or death may occur. components used in life-support devices or systems must be expressly authorized by zmd for such purpose. limited warranty the information in this document has been carefully checked and is believed to be reliable. however zentrum mikroelektronik dresden ag (zmd) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. the information in this document describes the type of component and shall not be considered as assured charac- teristics. zmd does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. this document does not in any way extent zmd?s warranty on any product beyond that set forth in its standard terms and conditions of sale. zmd reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.

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